Nagesh Ramavath
Placement Cell Coordinator| Ex-Intern @DRDO| Final-Year ECE @NIT Kurukshetra | VLSI Design, RTL, DV, PD Flow, DFT | Verilog/SV/UVM | ASIC/SoC Enthusiast
- Role
- Placement Cell Coordinator at Training And Placement Cell, Nit Kurukshetra
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Nagesh Ramavath
Final-year ECE student at NIT Kurukshetra and DRDO Ex-Intern with a strong interest in VLSI design and verification. Skilled in Verilog, SystemVerilog, UVM, RTL design, and familiar with PD and DFT fundamentals. Worked on digital design projects including a 1x3 router (RTL + UVM) and AHB–APB bridge. Exploring opportunities in RTL, DV, PD, and DFT roles.
Experience
Placement Cell Coordinator
Training And Placement Cell, Nit Kurukshetra
Jan 2026 — Present · Kurukshetra, IN
Education
National Institute of Technology, Kurukshetra, Haryana
Bachelor of Technology - BTech, Digital Communication and Media/Multimedia
Bhavita Junior College Devarakonda
Intermediate , MPC
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