Nagendra Babu

About Nagendra Babu

Engaged with cutting-edge technologies like TSMC 6nm and SMIC 12nm- Contributed to 2 successful tapeouts as a Physical Design Engineer- Proficient in various aspects including floor planning, placement, clock tree synthesis (CTS), routing, physical verification using Calibre DRC & LVS, static timing analysis (STA), timing closure, electromagnetic (EM) and IR analysis, and Formality-Skilled in hierarchical interface timing closure from partition to final timing closure- Utilized tools such as Innovus (Cadence), PrimeTime, StarRC, and Virtuoso-Possess a strong grasp of the RTL-GDSII flow-Demonstrated proficiency in physical verification, including DRC/LVS checks and layout verification against schematics-Familiar with standard cell architecture and proficient in designing layouts using standard cells-Proficient in scripting languages like TCL and Python-Solid understanding of logic synthesis.

Experience

1. Physical Design Engineer

   Sierraedge Ai

   Jun 2024 — Present · Bengaluru, IN

Education

• LOYOLA INSTITUTE OF TECHNOLOGY AND MANAGEMENT

  Bachelor of Technology - BTech

  2015 — 2018

• LOYOLA INSTITUTE OF TECHNOLOGY AND MANAGEMENT

  Master of Technology - MTech

  2018 — 2021