Nagaraju Bandari

About Nagaraju Bandari

As a Senior FPGA Engineer, I led the end-to-end design and validation of multiple FPGA-based systems, with a strong focus on high-speed data processing and protocol-level system integration. I was responsible for architecting and delivering robust, production-ready FPGA solutions, overseeing RTL design, simulation, synthesis, and board-level validation. I actively managed and mentored a team of engineers, ensuring technical alignment and timely execution across projects.My role included cross-functional collaboration with hardware, software, and verification teams to drive seamless integration. I was also involved in schematic reviews, design documentation, and preparation of critical deliverables such as Acceptance Test Procedures (ATP) and CCFDR (Component/Configuration/Functional Design Review) documents. My contributions spanned technical execution, project planning, and quality assurance, ensuring consistency and excellence across multiple development cycles.

Experience

1. Digital Design Engineer

   Centum Electronics Ltd.

   Jul 2021 — Present · Bangalore Urban, IN

   As a Senior FPGA Engineer, I led the end-to-end design and validation of multiple FPGA-based systems, with a strong focus on high-speed data processing and protocol-level system integration. I was responsible for architecting and delivering robust, production-ready FPGA solutions, overseeing RTL design, simulation, synthesis, and board-level validation. I actively managed and mentored a team of engineers, ensuring technical alignment and timely execution across projects.My role included cross-functional collaboration with hardware, software, and verification teams to drive seamless integration. I was also involved in schematic reviews, design documentation, and preparation of critical deliverables such as Acceptance Test Procedures (ATP) and CCFDR (Component/Configuration/Functional Design Review) documents. My contributions spanned technical execution, project planning, and quality assurance, ensuring consistency and excellence across multiple development cycles.Key Responsibilities: • Developed optimized RTL code for high-speed, performance-critical FPGA designs, ensuring efficiency and reliability across multiple complex projects. • Executed both I/O-level and full system-level integration, supporting seamless connectivity and functional alignment with hardware and embedded software systems. • Worked on advanced applications including hyperspectral imaging payloads, wideband digital receiver systems, and RF radar-based subsystems for signal acquisition and processing. • Utilized industry-standard tools and technologies, including Xilinx Vivado, ModelSim, Questa Sim, and Microsemi Libero for design, simulation, and implementation. • Integrated and validated multiple protocols and interfaces, such as: • High-speed data interfaces: sFPDP, JESD, DDR1/DDR4, ADCs/DACs, Flash, SRAM • Serial communication protocols: RS-422, RS-485, UART, SPI, I²C • Other key interfaces: Ethernet, SerDes, clock synthesizers, and more

Education

• JNTUH College of Engineering Hyderabad

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

• Kakatiya Institute of Technology & Science, Yerragattu Hillocks, Bheemaram, Hasanparthy, Warangal

  Master of Technology - MTech, VLSI and embedded systems

• Sri Saraswathi Vidhyaalaya Matriculation School

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2009 — 2013