Nagaraj Jaka
Senior Staff Engineer/DV Lead at Samsung
- Role
- Senior Staff Engineer Dv Lead at Samsung Semiconductor
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Nagaraj Jaka
My professional experience is in VLSI/Embedded services and working for the various semiconductor/embedded companies.Specialization includes • Functional Design and Verification, • Verilog/VHDL RTL coding, • Developing verification IP\'s using eRM and UVM, Test bench architecture• Coverage driven verification using HVLs like specman and syetem verilog • Gate level simulation. And other experience skills included are• Strong hands-on debug skills in a module/full chip.• Developed automated environment using Perl/Shell.• Good Knowledge in Code/Functional coverage.• Good knowledge in Regression, Random Regression, Coverage Driven Verification,• Functional coverage and self checking test benches.• Preparing good structured design documentation, Test plan, Test cases.• Knowledge in Test Description Language (TDL) generation and simulation. Technology Domains worked on includes wireless platforms like Ethernet/WLAN, Multimedia, OMAP, TI Debug architecture and embedded processors. Exposed to ARM and TI Mobile processors.Ethernet protocols : WLAN PHY/MAC Layer, 802.11a/b/g.Bus Protocols : USB, ATA,OCP, AMBA ATB, AXI3, APB, AHB.Debug & Trace : CoreSight Debug System and TI DebugSS.Processor : ARM Cortex, TI-OMAP Mobile.Project and Delivery Management- Managed multiple ASIC Design and Verification projects in VLSI Space including turnkey engagements with key Semiconductor customers- Leading the verification project team of 4 to 6 members in various skills like Design Verification- Delivering quality services and better solution for various projects.Focussing relentlessly on customer satisfaction, People Satisfaction and upgrading the relevant Technical skills by thinking and applying innovative ideas.
Experience
Senior Staff Engineer Dv Lead
Sep 2021 — Present · San Diego, CA, US
Education
Manipal University, Mangalore
Master of Science (M.S.), VLSI Design and CAD
2009 — 2011
Gulbarga University
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
1997 — 2001
Jawahar Navoday Vidyalay
Preschool & College, Science, Maths and Physics
1990 — 1997
Skills
- Pmp
- Application-Specific Integrated Circuits (Asic)
- Test Planning
- Process Automation
- Verilog
- Soc
- Vhdl
- System Verilog
- Verification Methodologies Erm and Uvm
- System on a Chip (Soc)
- Very-Large-Scale Integration (Vlsi)
- Qtp
- Specman-E
- Perl
- Scrum
- System Automation
- Etl
- System Testing
- Unix
- Soc & Ip Verification
- Data Warehousing
- Quality Center
- Software Project Management
- Test Management
- Integration
- Vlsi
- Testing
- Functional Verification
- Asic
- Resource Management
- Project Management
- Requirements Analysis
- Regression Testing
- Systemverilog
- Debugging
- Software Quality Assurance
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.