Nagalohitha Chandupatla
Soc Logic Design Engineer @Altera
Austin, TX, US
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jan 2025 — Present
Soc Logic Design Engineer @Altera
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Austin, TX, US
EDUCATION
2011 — 2015
GITAM Deemed University
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering
2016 — 2018
San José State University
Master's degree, Electrical and Electronics Engineering
SKILLS
VerilogMatlabCMicrosoft OfficeC++Microsoft WordMicrosoft ExcelResearchWindowsJavaProgrammingHtmlEnglishPublic SpeakingSqlJavascriptTeamworkCssPythonCore JavaStatic Timing AnalysisEdaRtl DesignSynopsys ToolsCadence VirtuosoPhysical DesignLinuxApplication-Specific Integrated Circuits (Asic)Very-Large-Scale Integration (Vlsi)ModelsimXilinx IseHardware ArchitectureOperating SystemsComputer ArchitectureUnixSystem on a Chip (Soc)Computer HardwareSemiconductorsPerl
ABOUT NAGALOHITHA CHANDUPATLA
SoC design engineer with 8+ years of experience in FPGA and ASIC Design. Strong technical knowledge in static timing analysis, timing model generation, full chip timing integration, and correlation with a proven track record of optimizing designs and improving performance.
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