Muthurasu Sivaramakrishnan

About Muthurasu Sivaramakrishnan

9 years of professional experience in Verification of IP\'s,/SoC and Development of Design Verification Environments.*Very Good experience in creating testbench architecture, Building Verification Envirnments and Implementation in System Verilog HVL from scratch for required standard/specification.*Very Good experience in block level/IP level verification of complex multi-million gate designs.*Strong Knowledge of UHS-II (SD4.0), SD Memory, eMMC and SDIO Host/Device.*Developed architecture, successfully designed and implemented SD Host New Test Environment.*Ownership of SD host System Model(AHB/AXI/OCP) and Device Model(SD,eMMC,SDIO and MSPro).*Achieved 100% functional coverage on block level module using SVA and PSL assertions.*Achieved 100% code coverage, block coverage and FSM coverage on block level module by writing directive tests.*Worked couple of projects in SoC Design Verification. Integrated UVM/OVM VIP\'s to the SoC verif. environment.*Experience in scripting languages like PERL. Created few scripts to reduce manual efforts.* 6 months experience in GPU Performance Emulation testing using Cadence Palladium Emulator.Specialties:* Verilog, System verilog for Verification. OVM/UVM and C/C++ based Verification envirnonment* System verilog and PSL for Assertions, Randomization.* Verilog for RTL Design.* Protocols - AHB, AXI, UHS-II, SD4.0, eMMC Host and Device controllers(SDCC, eMMC)* Cadence -Verilog-XL, NC – Verilog, Synopsys-VCS, Modelsim for RTL/netlist simulation. Debussy-Verdi* Synopsys – DC/PC for Synthesis.* Atrenta - Spyglass (version 4x)* Cadence Palladium Emulator(STB)* CVS, Clearcase and Perforce for Data management* Bugzilla for filing bugs* Testlink for the management of test environment* Frame Maker for Documentation.

Experience

1. Soc Design and Verification Engineer

   Intel

   Jan 2015 — Present

Education

• Anna University Chennai

  BE, ELECTRONICS AND COMMUNICATION

  2002 — 2006

• Anna University Chennai

  B.E, Electronics and Communication

  2002 — 2006

• Govt. Hr. Sec. School, Uthumalai, State Board of

  Higher, Education; 12th STD

  2000 — 2002

• Govt. Hr. Sec. School, Uthumalai, State Board of

  +2, Mathematics and Computer Science

  1999 — 2000

• Anna University Chennai

  Bachelor's Degree, Electrical, Electronics and Communications Engineering

  2002 — 2006

Skills

• Cadence
• Usb
• Mipi
• Pcie
• Modelsim
• Soc Verification
• Open Verification Methodology
• Fpga
• Asic
• Axi
• Perl
• Eda
• Xilinx
• Systemverilog
• Amba Ahb
• Logic Synthesis
• System Verilog
• Rtl Design
• Verilog
• Integrated Circuit Design
• Specman
• Vlsi
• Spyglass
• Physical Design
• Ip Verification
• Xilinx Ise
• Asic Design Verification
• Tcl
• Cadence Virtuoso
• Rtl Coding
• Functional Verification
• Functional Coverage
• Formal Verification
• Ip Addressing
• Vhdl
• Simulations
• Arm
• Timing Closure
• Ncsim
• Soc