Musala Reddy

About Musala Reddy

I have worked for different technologies(350,180,130,90,65,40,28nm) for dfferent foudries like TSMC,CSM,UMC,TOWER,AMS,IBM,GSMC,SMIC,FUJITSU•Expertise Writing scripts to create Parameterized cells and test these Pcells by performing a Layout versus Layout check, drc checks and parametric checks.•Creation of Extraction Rule files, LVS rule files and performing device extraction tests to ensure netlisting of all required spice parameters.•Expertise developing complex layout like DFE,VGA,CDR,CTLE,LC-PLL(12.5G,10G),High speed serdes macrors buffers,ADC,DAC,DLL,BGR,VR,COMPARATORS,MDAC,•Expertise developing layout of different standard IO interfaces like SSTL,LVDS-TX,LVDS-RX,HSTL,CML•Expertise developing layout if IO libs, standard cell libs and qualifying libs to use in auto place and route tools•Expertise developing critical macro like TCON,HIGH SPEED SERDES GPON,EPON,XGPON,HDMI,USB,PCI,ETHERNET•Expertise floorplanng, power routing, IR drop analysis, EMI and ESD scheme for macro and chip top•Supervision and assistance for other Designers in development, floor planning, and scheduling•Expertise executing physical verification in the form of,LPA,EMIR,DFM, DRC, LVS, ESD,LVL,SVS & ERC for layouts up to chip level, and perform debug from results•Expertise of Scripting experience (Perl,Tcl/tk Shell Scripting) •Design experience of place and routing using encounter for top level macro, CTS, special routing•Expertise working with different kind pad arrangement like CUP and non-CUP,inline,stagered,two tier,tri-tier, flip-chip technologies •Expertise to work in an international team and a dynamic environment.•Expertise to learn and adapt to new tools and methodologies •Expertise layout automation and layout optimization •Expertise to lead a sub-team to complete a full-scale test chip development,from floor plan to tapeout•Expertise to provide technical support/guidance to engineers

Experience

1. Analog Layout Manager

   Texas Instruments

   Feb 2017 — Present · Bengaluru, IN

Education

• Govt Institute of Electronics Secunderabad

  Dipolma, Electronics and Computers

  2000 — 2003

• Jawaharlal Nehru Technological University

  B-tech, Computer Science

  2004 — 2008

Skills

• Fpga
• Asic
• Pll
• Verilog
• Physical Verification
• Soc
• Layout Versus Schematic (Lvs)
• Rtl Design
• Integrated Circuit Design
• Ic Layout
• Testing
• Perl
• Eda
• Usb
• Modelsim
• Mixed Signal
• Tcl
• Analog
• Static Timing Analysis
• Physical Design
• Dft
• Drc
• Timing Closure
• Vlsi
• Cadence Virtuoso
• Cmos
• Analog Circuit Design
• C
• Lvs
• Cadence
• Ic
• Low-Power Design
• Serdes