Muruganantham M.

About Muruganantham M.

15+ years of experience in ASIC front end Design Verification • Hands on experience in RTL, power aware RTL with UPF, Gate Level Simulation Timing, No-Timing and power aware GLS simulation (Netlist + UPF).• Experience in system Verilog and UVM verification methodology• Experience in IP Level verification, Functional Coverage & ABV (Assertion) • Experience in TB development Knowledge in PCIE PHY Layer (PCS).• Experience in ARM Architecture Cortex-M0, M3 and A9, A15 with ASM, C- Coding.• Experience in ARM & DSP Architecture verification in Power Aware RTL Simulation • Experience in Silicon test vector failures – JTAG, BSDL & QDSS vectors

Experience

1. Staff Electrical Engineer (Dv)

   Renesas Electronics

   Jan 2024 — Present · US

   Working As Staff Electrical Engg - Multi Phase VR Controller Design Verification team.

Education

• Tmt Elizabeth polytechnic, Technical Board Tamilnadu

  Diploma, Electronics and Communication Engineering

  1999 — 2002

• Kurunji College of Engineering Technology

  BE, Electronics and Communication Engg

  2002 — 2005

• RV College Of Engineering

  Master of Technology - MTech, VLSI Design and Embedded System