Muriki Maniteja
Design and Verification Engineer at BITSILICA | Formerly trained at T. A. S. K. |VLSI | DIGITAL ELECTRONICS | VERILOG | System Verilog | UVM |Green electronics | Python | Electronics and communications engineering
- Role
- Design and Verification Engineer at BITSILICA
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Muriki Maniteja
Hello! I am a recent graduate actively looking for an opportunity of an entry level Design Verification engineer role in a highly committed organization and develop various test cases for verifying the design and ensure there are minimum number of errors as much as possible. I am good at Digital electronics, Verilog, System Verilog and UVM methodology. Projects I have done-Design of a PLL using high frequency Voltage Controlled Ring Oscillator in Cadence Virtuoso in 45 nm technologyDesign of a 64- bit Vedic Multiplier using Vedic Sutra \"Urdhvatiryagbhyam\" in Xilinx Vivado using Verilog HDL. I want to utilize my knowledge to strengthen the value of the firm by verifying various RTL codes for designing high efficient products with minimum errors and faults.Curious to connect with growing minds and organization.
Experience
Design and Verification Engineer
Sep 2025 — Present · Hyderabad, IN
Education
Government polytechnic,Warangal
High School Diploma
2018 — 2021
Nalla Narasimha Reddy Education Society Group of Institutions
Bachelor of Technology - BTech
2021 — 2024
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