Muralidhara K Bhadregowda

About Muralidhara K Bhadregowda

ASIC verification at the block level and SoC level.Involved in complete product verification cycle from setup of the simulation environment, development oftest plans, test benches, writing random and directed tests, coverage analysis and gate-level simulations.Proficient in HDL languages like Verilog and System Verilog.Experience in architecting and developing multiple test benches both at the module level and SOC levelwith easy portability in System Verilog using UVM methodology.Experience in writing assertions in SVA for both simulation and formal verification.Experience in writing metric-driven verification using vManager and vPlan.More than 5 years of DDR Controller verification experience across multiple memory classes likeDDR3/4/5 and LPDDR3/4/5.Experience in working with complex Coherent Mesh Network like CMN600.Formal verification using Jasper, with experience in writing end-to-end checkers using various abstractiontechniques.Bringing up designs in Emulation (Palladium), running and debugging test cases and writing BFMs forpalladium.Experience in writing tests for power management verification at the chip level.Run and debug tests in zero-delay and gate-level simulations.Hands-on experience in Automated Test Equipment (ATE).Verilog System Verilog with VMM and UVM methodologies, Vera, SVAPerl, Python, Assembly (ADI Blackfin Processors)APB, AHB, AXI3/4, CHI, DDR3/4/5, LPDDR3/4/5

Experience

1. Principal Member of Technical Staff

   Rivos Inc

   Jun 2022 — Present · Austin, TX, US

Education

• National Institute of Technology Karnataka

  Bachelor of Technology (B.Tech.)

  2001 — 2005

Skills

• Vmm
• Uvm
• Rtl Design
• Verilog
• Ncsim
• Functional Verification
• Amba Ahb
• Open Verification Methodology
• Axi
• Perl
• Asic
• Soc
• Vlsi
• Simulations
• Systemverilog