Murali Paila

Analog Layout Engineer

Role
Analog Layout Engineer at KriSemi Design Technologies
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers

About Murali Paila

I have a Good Experience in I&O layout Design. Good understanding of designing Analog and Digital Layouts using CMOS and FinFET process. Good Knowledge in CMOS fundamentals. Good Knowledge in Layout related effects such as Latch UP, Crosstalk & EM & IR. Debugging of DRC in different technologies(TSMC 2nm, TSMC 3nm, TSMC 7nm, TSMC 16nm & TSMC 28nm) & LVS related verification issues.

Experience

  1. Analog Layout Engineer

    KriSemi Design Technologies

    Aug 2023 — Present · Hyderabad, IN

Education

  • AANM&VVRSR POLYTECHNIC

    Diploma of Education, Electrical and Electronics Engineering

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Murali Paila — Analog Layout Engineer at KriSemi Design Technologies in Hyderabad, TG, IN | Unifers