Murali Mohan P.
Design Verification Leadership, Power Management Division @onsemi
- Role
- Design Verification Management & Leadership at onsemi
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Murali Mohan P.
A motivated and enthusiastic Design Verification (DV) engineer with 15 years of experience. Strong understanding of ARM CortexM3/R5/A9/A57/A53 based Processor subsystem/SoC verification, Gate Level Simulation and Coverage closure. TECHNICAL SUMMARY• Good understanding of CortexA57/A9/CortexM3/Cortexr5 architecture• Good knowledge of Coresight logic used for CortexA9/CortexM3/CortexA57• Exposure to Gate level simulations• Toggle Coverage Closure• FPGA net list simulation• SoC connectivity using Cadence formality tool(IFV)• Good knowledge on HAPS62 emulation platform and debugging tools Trace32 and D-stream• Benchmarking of arm processor using EMBC coreMark.• Simulation and emulation of U-boot
Experience
Design Verification Management & Leadership
Feb 2025 — Present · US
Education
CEDTI,Aurangabad
M.Tech, Electronics Design and Technology
2005 — 2007
Harvard Business School Online
Certification Program, Leadership Principles
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