Munish Aggarwal

About Munish Aggarwal

Strong Experience in Scan insertion using different methodology of DC-Compiler like Scan Compression/Core 1500 wrapper with OCC in the Design.• Strong Experience in ATPG pattern generation using TMAX and DRC debug for transition model and stuck-at model includes DFTMAX and Ultra Compressor LBIST flows.• Strong Experience in Gate Level simulations includes design debug and pattern validation using NCSIM/VCS.• Strong experience in On Chip Clocking implementation includes clock merging for TF model and Scan Architecture Design.• Formal Verification on the pre-DFT netlist Vs post-DFT netlist.• Experience in MBIST implementation and its verification.Specialties: Verilog, ASIC, DFT, SoC Design, Scan Insertion/Pattern Generation and Validation for DFTMAX and Ultra Compressor(LBIST)

Experience

1. Senior Design Engineer

   NVIDIA

   May 2016 — Present

Education

• New Yashoda Public School

  Secondary, 2003

  2002 — 2003

• Seth Jai Parkash Mukand Lal Institute of Engineering & Technology

  B.Tech, Electronics & Communication

  2005 — 2009

• Dhirubhai Ambani institute Of Information and Communication Technology, Gandhinagar

  M.Tech(ICT), VLSI & Embedded System

  2009 — 2011

• New Yashoda Public School

  Senior Secondary, Physics, Chemistry, Maths

  2003 — 2005

Skills

• Verilog
• Vhdl
• Dft
• Vlsi
• Atpg
• Lbist
• Hardware Architecture
• Tetramax
• System on a Chip (Soc)
• Xilinx Ise
• Soc
• Tcl
• Test Validation
• Scan
• Field-Programmable Gate Arrays (Fpga)
• Modelsim
• C
• Fpga
• Asic
• Microelectronics
• Very-Large-Scale Integration (Vlsi)
• Application-Specific Integrated Circuits (Asic)
• Cadence
• Dft Compiler
• Static Timing Analysis