Munir Razzaque

About Munir Razzaque

Active TS/SCI Clearance with Counter-Intelligence Polygraph (CI)Design Verification Engineer with extensive experience in hardware verification and solid background in computer architecture. Known for verification testbench development, methodology specification, test-plan development and execution. Excellent problem solving skills with expertise in block-level and system-level functional verification, design integration, and tools development. Particularly effective at integrating technical solutions with cross-cultural teams. Hardware design verification • Gate netlist verification • Hardware emulation Testplan/Testbench development • Computer Architecture • Design integrationLanguages: UVM, OVM, SystemVerilog, Verilog, Python, C, C++, STL, MIPS and x86 AssemblyArchitecture: ARM, PowerPC, MIPS, Intel x86, AMDx86-64, MIPS, AMBA, JTAG, SoCTools: Xcelium, Questa, Jasper, Matlab, Palladiam, Perforce, LSF, emacsEmail: m••••••••@yahoo.comTelephone: 51••••••18

Experience

1. Soc Verification Lead

   Northrop Grumman

   Sep 2015 — Present

   Define and develop SoC design and verification methodologies based on new hardware DSL: CHISEL (Constructing Hardware In a Scala Embedded Language). • Chisel provides powerful abstraction which brings hardware design closes to functional programming, and significantly speeding up hardware development.Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex RTL designs.• Develop and drive verification plans• Generate constrained random and directed tests to implement verification plan• Run simulations and debug issues across hardware and software • Create verification test bench components to drive/monitor and check design• Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes• Create automated verification flows for productivity improvement.• Active security clearance

Education

• The University of Texas at Austin

  BSEE, Electical & Computer engineering

• The University of Texas at Austin

  MSEE, Computer Engineering

Skills

• Power Management
• Vlsi
• Debussy
• Cache Coherency
• Tcl
• Analog
• Linux
• Soc
• Algorithms
• Operating Systems
• Gate Netlist
• Systemverilog
• Uvm
• Functional Testing
• Perl
• Low Power Systems
• Test Case Generation
• Processors
• Vhdl
• Simulations
• Assembly
• Coverage
• Emulation
• Debugging
• Ip
• Verilog
• Silicon
• Hardware
• Integration
• Ovm
• C++
• Computer Architecture
• Architecture
• Engineering
• Cpu Design
• Microprocessors
• Rtl Design
• Vcs
• Multiprocessing
• Fpga