Munagala Prapulkumar

WORK HISTORY

EDUCATION

ABOUT MUNAGALA PRAPULKUMAR

ANALOG LAYOUT\' EngineerExperienced Analog Layout Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Design Rule Checking (DRC), Analog Circuit Design, Standard Cell, Virtuoso, and Layout Versus Schematic (LVS). Strong engineering professional with a MTech focused in VLSI from Chirala Engineering College.* knowledge on CAP,RES* knowledge on Conductor,instulator, Semi conductor* knowledge on BJT,Mosfet And finfet* knowledge on Tool : Cadance Virtuoso* knowledge on Verification Tool : Calibre* worked on TSMC 2nm(GAFET),7nm, 12nm & 16nm(FinFET),40nm(Planer)* worked on L,XL and EXL Layout EditingFabrication:* knowledge on Cmos FabricationLayout Topics:* knowledge on Electromigration* knowledge on IR Drop* knowledge on Latch up* knowledge on Cross talk* knowledge on Shielding* knowledge on well proximity * knowledge on Antenna Effect* knowledge on Locus, STI & DTI* knowledge on Length of Diffusion* knowledge on Channel length Modulation* knowledge on Surface Scattering* knowledge on velocity saturationTool Techniques* knowledge on Matching Technique(Interdigitation, Common Centroid)* knowledge on DeepNwell Devices.* knowledge on floor planning* knowledge on signal Routing* knowledge on Double Patterning( Masking) Digital Cells* knowledge on Logic gates(Inv,Nand,Nor,And,Or,Xor,Xnor).* knowledge on Latches* knowledge on Multiplexers Verification Technique* knowledge on DRC ( Design Rule Check)* knowledge on LVS (Layout Vs Schematic) Projects1. Standard cells2. OP AMP(single stage & 2 stage)3. Comparator4. Adc_baisgen5. Bi-GPIO 6.Vibrio7.22 pads8.Glitch Detector9. 9B5X10. 9BAB