Mukesh Bhartiya
Senior Technical manager with proven track record of IP/SOC delivery, Logic Synthesis, STA and low power sign-off
- Role
- Engineering Director Intel Foundry Services at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Mukesh Bhartiya
Senior Technical manager with twenty-five years of proven track record in SoC, ASIC IP Design delivery, Logic Synthesis, Static Timing Analysis and low power sign-offSkills: Technical Program management, Strategic Hiring, Coaching, Mentoring, Team Building, High level executive presentations, Stakeholder management, Strong communication skills and Customer First mindset. Technical Skillset: Linting, CDC, Synthesis, Static Timing Analysis, Low power implementation and Sign-offEDA Tools: VCS, Spyglass Lint, Design Compiler, Power Compiler, Fusion Compiler, Primetime-SI, PrimepowerHDL\'s: VHDL, Verilog, System VerilogMethodologies: UVMScripting Languages: Perl, TCLProtocol: AHB-Lite/AMBA, APBAwards/Recognitions: Intel Foundry Services level Group Recognition for delivering DFY methodology (2023) Intel Labs Gordy award winner of “Excellence in Leading People & Teams” category (2021) Winner of Intel Labs most prestigious “Gordy Awards” in technical category (2013/2018) Multiple “Departmental Recognition Awards” for IL SoC projects “Manager Of The Year”, Synopsys India (EDA) Software Pvt. Ltd, 2010 “Outstanding Technical Contributor Award”, Synopsys India (EDA) Software Pvt Ltd. 2005 “Performer Of The Year” for Outstanding contributions, D’gipro Systems Pvt. Ltd, 2001Certification:Semi-Conductor Automotive Functional Safety Professional certified by SGS TUV: 20••••24
Experience
Engineering Director Intel Foundry Services
Nov 2021 — Present · Bengaluru, IN
Leadership role focused on SoC Timing, EMIR and power Sign-Off. Managing E2E TFMs for all SoC projects with IFS India. Defining STA methodology for Intel3 and 18A
Education
Indian Institute of Management Bangalore
EGMP
2007 — 2008
B. M. S. College of Engineering
Engineer’s Degree, Telecommunications
1994 — 1998
Skills
- Soc
- Communication Skills
- Eda
- Asic
- Static Timing Analysis
- Tcl
- Vlsi
- Ic
- Semiconductors
- Verilog
- Integrated Circuit Design
- Rtl Design
- Debugging
- Physical Design
- Low-Power Design
- Timing Closure
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