Somasekhar Mamidanna
Technical Lead, Senior Manager
- Role
- Asic Digital Design Sr Manager at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Somasekhar Mamidanna
Verification expert with vast experience in handling IP, sub systems verification and drive projects from end to end.Experienced in -Team ManagementBlock level and Chip level functional VerificationSV/UVM TB ArchitectureTestplan writingFunctional Validation Functional Validation specs writingCode Reviews andTeam Lead activitiesSelf initiated internal SV/UVM and TB Arch training(s) to the teamDomains of Expertise:Networking Domain (Ethernet), MAC, PCIe, AXI, APB, DFI, DDRSpecialties: Arch Understanding of - Ethernet Switches, Host Subsystems (PCIe), DDR-PHY, DMAHDLs: VHDL, VerilogHVLs: System Verilog (UVM)Scripting Languages: PERL, TCL
Experience
Asic Digital Design Sr Manager
Feb 2025 — Present · Hyderabad, IN
Driving Next Gen DDRPHY Verification
Education
International Institute of Information Technology Hyderabad (IIITH)
M.Tech, VLSI & Embedded Systems
2005 — 2007
Vardhaman College of Engineering
BTech, Electronics and Communication Engineering
2001 — 2005
Skills
- Debugging
- Systemverilog
- Very-Large-Scale Integration (Vlsi)
- C
- Soc
- Gigabit Ethernet
- Pcie
- Ethernet
- Asic
- 10g Ethernet
- Tcl
- Ic
- Verilog
- Rtl Coding
- Rtl Design
- Vhdl
- Simulations
- Carrier Ethernet
- Application-Specific Integrated Circuits (Asic)
- Perl
- Vlsi
- Functional Verification
- Processors
- Uvm
- Integrated Circuits (Ic)
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