Mrutyunjay Chauhan
Senior Soc Ip Verification Engineer-ii @Microchip Technology Inc.
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WORK HISTORY
Senior Soc Ip Verification Engineer-ii @Microchip Technology Inc.
Cambridge, GB
EDUCATION
Gujarat Technological University (GTU)
Bachelor of Engineering (B.Eng.), Electronics and Communications Engineering
Sandeepani School of VLSI Design
professional development course, VLSI Design And Verification
ABOUT MRUTYUNJAY CHAUHAN
B.E in E.C. With 9+ years of experience in VLSI industry. Skilled in Universal Verification Methodology (UVM), System Verilog, RTL coding,Debugging,Digital design,FPGA(Xilinx) & C.Have good knowledge and interest in core verification which involves processor with memory and various peripherals.Strong engineering professional with a Bachelor of Engineering (B.E.) focused in Electronics and Communications Engineering from GEC,MODASA,GUJARAT. Have done professional development course in VLSI Design & Verification from Sandeepani school of VLSI design.==> Have been part of two SOC projects from coding of testbanch to coverage closure.Which involves working on soc boot & make file flow setup, setting up UVM testbench environment,developing c & sv test cases & sequences for core,peripherals,memory etc.==> Also developed RAL model & coverage model with coding and analysis targeting 100% code & functional coverage across the all soc modules.==> Have worked on Integration of various vendor VIPs and porting the test cases & sequences into the soc environment.==>\'x\' propagation & GLS simulations regression Debugging.==> Worked on verification of various memory modules like shared memory & OTP memory in the soc.==> Developed c test cases for various soc peripherals like IOSF,AVALON, GPIO,DMA,SPI,I2C,UART,TIMERS,MEMORIES,etc. which includes programming of peripheral, generating interrupts, data transfer using DMA\'s.==> scripting languages known are linux shell bash script and python.
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