Mrudula Yedavally
Graphics Logic Verification Engineer @Cypress Semiconductor Corporation
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WORK HISTORY
Graphics Logic Verification Engineer @Cypress Semiconductor Corporation
Munich, DE
Functional Verification of Timestamping Unit in AURIX™ TC4x family of automotive microcontrollers (MCUs) from Infineon Technologies (ongoing).Experience:SystemVerilog and UVM Verification (SV/UVM)Developing Verification Requirements and Verification Plan from the Hardware Architecture DocumentConstrained Random Verification (Configuration knobs)Scoreboard - Checkers, Reference ModelRegister Verification - UVM RAL, Integration of Register Adapter with Register Access Interface in AURIX, Register CallbacksExperience with Testbench GeneratorsVIP IntegrationTools:Cadence Xcelium, Simvision, vManagerGIT
EDUCATION
Technical University of Munich
Master of Science (M.Sc.), Communications Engineering
Goethe-Zentrum, Hyderabad
Level A1, German Language and Literature
Goethe-Zentrum, Hyderabad
Level B1, Germanic Languages, Literatures, and Linguistics
Manipal Institute of Technology
Bachelor of Engineering (BE), Electronics and Communication Engineering
FIITJEE Junior College
High School, PCM
Centre for Development of Advanced Computing
Post Graduate Diploma, Embedded Systems Design
Goethe-Zentrum, Hyderabad
Level A2, German Language and Literature
SKILLS
ABOUT MRUDULA YEDAVALLY
Design Verification / Functional Verification Engineer with close to 5 years of experience in IP and Subsystem Design Verification in SystemVerilog and UVM, constrained random verification, SystemVerilog Assertions with strong communication and collaboration skills. Currently working as a Graphics Logic Verification Engineer at Cypress Semiconductors GmBH (now Infineon Semiconductors, part of Infineon Technologies) in Munich, Germany. Previously worked as an ASIC Developer at Ericsson AB in Lund, Sweden, involved in the verification of Interface IP blocks in Baseband ASICs of the Ericsson 5G NR portfolio. Graduated from Technical University Munich with a Masters of Science degree in Communications Engineering with my Master\'s Thesis at Infineon Technologies Austria AG.Fields of study during my masters included System-on-Chip Design Technologies, Digital Circuits, IC Design, Electronic Design Automation and FPGA Design and Development.Prior experience with Embedded Systems in C, C++, Python and Embedded C through an Internship in development of a LoRa Sensor Node at Fraunhofer AISEC, Munich. Love travelling, and have great international multicultural experiences living and working in 4 countries. Also like learning new languages - have intermediate proficiency in German (B2), beginner proficiency in Swedish (A2) and fluent in English, Hindi and Telugu.
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