Mohammad Rafiee

Microelectronic Packaging Design Engineer @Sanmina

Ottawa, ON, CA

IC Packaging Design Engineer with a comprehensive skill set spanning the entire semiconductor packaging spectrum. Proficiency in design, FEA/CFD analysis, process engineering, manufacturing, testing, and reliability of semiconductor packaging projects such as flip-chip, wire bonding, BGA, TSV technology, Silicon Photonics, DSPs, ASICs, 2.5D, and stacked die 3D packages. I excel in mechanical, thermal, and electrical simulations using ANSYS Mechanical, IcePak, HFSS, and SIwave. My extensive experience with Chip-Package Interaction (CPI), CFD/FEA thermal design and electronic reliability enables success in assembly, mechanical, thermal and electrical performance of microelectronic packages, addressing warpage, stress, Solder Joint Reliability (SJR), electronic cooling, and signal integrity (SI), power integrity (PI). My deep knowledge of IC packaging from ideation to prototype and production for high-performance interconnect projects, combined with process engineering, Surface Mount Technology (SMT), flip-chip die attach, and various manufacturing methods, positions me as a key contributor to optimizing product reliability and performance. I have developed innovative IC packaging designs, optimized process engineering and manufacturing, conducted detailed ANSYS simulations to predict and analyze mechanical stresses and thermal profiles, and validated these simulations with experimental analysis. My efforts contributed to the high quality, reliability and performance of advanced microelectronic packages. My ability to clearly explain complex technical concepts to both technical and non-technical audiences is a key asset in my professional career. My broad expertise is supported by strong skills in CAD (SolidWorks and AutoCAD), proficiency with EDA tools like Cadence Allegro Advanced Packaging Designer (APD) and Cadence PCB Editor.

University of Ottawa

Doctor of Philosophy (PhD), Mechanical Engineering