Mike Clinton

About Mike Clinton

Over 25 years experience in stand-alone and embedded memory (DRAM, MRAM and SRAM) design projects. Lead designer for multiple 64Mb and 256Mb DRAM products qualified and manufactured by IBM/Toshiba/Nanya/Infineon. SRAM design experience with Texas Instruments at 65nm, 45nm and 32nm technology nodes. Architect for aggressive power management techniques implemented in TI SRAM compiler memories starting at 65nm. Recognized industry expert in variation tolerant SRAM circuit design techniques.Proven record of solving problems and breaking down technical barriers by building teams and working across organizational boundaries.Experience working with teams in various geographic locations throughout the US, Japan. Taiwan, India and Europe and achieving on-time, high quality products and results.* Technical program committee member and joint technology/circuits rump session co-organizer for the 2009 VLSI Circuits Symposium (Kyoto, Japan).* Invited speaker Southern Methodist University, CS/EE forum to give talk on deep sub-micron design challenges (Dallas, TX - Jan. 2009).* Invited speaker at the Dallas chapter of Circuits and Systems, to discuss SRAM design and variability (Dallas, TX - July 2008)* Microprocessor Forum presenter (“Transistor Variability in Nanometer-Scale Technologies”) at the International Solid-State Circuits Conference (ISSCC)(San Francisco, CA -Feb 2008).* Speaker at a C2S2 (Center for Circuits and Systems Solutions) Workshop on SRAM design held at the Massachusetts Institute of Technology (Cambridge, MA - Oct 2007).Specialties:* Panelist for the technology session (“Who will keep SRAM scaling alive by 2012: Designers or Technologists?”) at the VLSI Technology Symp.(Honolulu, HI - June 2008).* Short Course presenter (“Design for Variability in Logic, Memory and Microprocessors”) at the VLSI Circuits Symp.(Kyoto, Japan - June 2007).* Tutorial presenter (“Anatomy of Variability and Making “Variation Tolerance” Vaccine in Nanometer Technologies”) at the Design Automation Conf.(DAC)(San Diego, CA - May 2007).

Experience

1. Director

   台積電

   Jan 2016 — Present · Austin, TX, US

Education

• Lehigh University

  Bachelor of Science (BS), Electrical and Electronics Engineering

  1978 — 1982

• University of Vermont

  MSEE, Device Physics

  1991

Skills

• Dram
• Processors
• Cmos
• Circuit Design
• Asic
• Embedded Systems
• Eda
• Sram
• Memory Test
• Low-Power Design
• Power Management
• Yield
• Microprocessors
• Analog