Mounika Valisekka
Design Verification Engineer | RTL Design | SystemVerilog • UVM • VHDL • Verilog • FPGA/ASIC | Master’s in ECE, University of Florida
- Role
- Design Verification Engineer at Steck Systems, Inc
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EducationView LinkedIn profile
About Mounika Valisekka
I recently earned my Master’s in Electrical and Computer Engineering from the University…
Experience
Design Verification Engineer
Present
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