Mounika N
Memory Layout Design Engineer
- Role
- Memory Layout Design Engineer at IBM
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Mounika N
Worked on TSMC 5nm, 7nm, 28nm, 180nm and FDSOI 22nm technologies. I\'m interested in memory layout and circuit designs.
Experience
Memory Layout Design Engineer
Feb 2022 — Present · Bengaluru, IN
Education
Nitte Meenakshi Institute of Technology
Bachelor of Engineering - BE, ECE
2014 — 2017
Jindal jubli high school
SSLC
2007 — 2011
M.N.Technical Institute - India
diploma, Electronics communication Engineer
2011 — 2014
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