Mohsen Nader Tehrani

About Mohsen Nader Tehrani

Senior Principal DSP Architect & Systems Engineering Leader with 12+ years of experience designing, validating, and deploying mission- and safety-critical systems across data-center interconnects, high-speed wireline and optical communications, and autonomous sensing platforms- Architecture owner and technical authority for end-to-end system definition, performance and safety sign-off, and long-term technology direction, spanning PAM4 and coherent optical interconnects, SerDes-based wireline links, and LiDAR-class sensing systems- Experienced technical leader and manager driving cross-functional execution across DSP, digital design, firmware, mixed-signal, perception, software, test, and safety teams, including technical planning, roadmap definition, prioritization, and mentorship, while aligning engineering execution with product and safety objectives- Deep expertise in advanced DSP architectures for data-center and AI-scale systems, including- High-speed wireline & optical interconnects (PAM4, coherent optics, SerDes)- 400G+ per-lane DSP and FEC (Reed-Solomon, BCH, soft-decision metrics)- Adaptive equalization, synchronization, detection, estimation, and control loops- Electrical and optical channel modeling, including nonlinear impairments- Fixed-point, hardware-efficient DSP for ASIC and SoC implementations- Strong systems-level experience in sensing and perception, including LiDAR and optical sensing pipelines, with ownership of real-time processing architectures, sensor/compute trade studies, and system sign-off using simulation, lab, and field data- Owner of system sign-off frameworks, verification and validation strategies, and root-cause analysis for performance and safety risks across both data-center interconnect and autonomous sensing domains; contributor to forward-looking architecture trade studies, including DSP/ML co-design- PhD in Electrical Engineering with strong programming and data-analysis skills in Python, MATLAB, and C/C++, plus working knowledge of Verilog RTL and HLS, enabling effective algorithm-to-hardware transfer, RTL assessment, post-silicon tuning, and production deployment- Most effective in roles requiring technical vision, senior-level mentorship, and delivery of production-scale systems meeting the highest standards of performance, reliability, and safety for AI infrastructure, data-center networks, and autonomous platforms.

Experience

1. Technical Lead Signal Processing Engineer

   Aurora

   May 2021 — Present · Mountain View, CA, US

Education

• Isfahan University of Technology

  Master's Degree, Communication Systems

  2006 — 2009

• University of Waterloo

  Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering

  2009 — 2013

• Isfahan University of Technology

  Bachelor's Degree, Communication Systems

  2002 — 2006

Skills

• Matlab
• Simulink
• Simulations
• C++
• Latex
• Signal Processing
• Mathematical Modeling
• Optimization
• Mathematics
• Algorithms
• Vhdl
• Image Processing
• Verilog
• Artificial Intelligence
• Digital Signal Processors
• Pattern Recognition
• Programming
• C
• Pspice
• Numerical Analysis
• Fpga
• Digital Signal Processing
• Rf
• Xilinx
• Spectrum Analyzer
• Pcb Design
• Mimo
• Hardware Architecture
• Lte