Mohit Chauhan

About Mohit Chauhan

I am a Physical Design Engineer with hands-on experience of delivering CPU cores at 4nm to 1.4nm process nodes for a leading semiconductor company. I specialize in ASIC backend design, covering Floorplanning, Powerplanning, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Timing Closure, ECO, and Physical Verification Signoff (DRC/LVS/DRV).I have successfully driven blocks of over 1.2 million instances, implemented complex multi-voltage power domains, optimized IR-drop-aware power grids, and reduced RTL-to-GDS runtime by 50% through innovative design improvements. Proficient in EDA tools including Fusion Compiler, PrimeClosure, IC Compiler II, PrimeTime, Calibre, and working knowledge of Tcl scripting.I am passionate about high-performance, low-power SoC design and thrive in cross-functional teams ensuring seamless handoff from RTL to Tape-in. Always eager to adopt next-generation design methodologies and contribute to faster, more efficient product tapeouts.

Experience

1. Cpu Physical Design Engineer

   Intel

   Jul 2021 — Present · Bengaluru, IN

Education

• Harcourt Butler Technical University

  Bachelor of Technology - BTech, Electronics Engineering

  2015 — 2019

• Indian Institute of Technology (Banaras Hindu University), Varanasi

  Master of Technology - MTech, Microelectronics(VLSI)

  2019 — 2021