Mohd Muktadar Mohiuddin

About Mohd Muktadar Mohiuddin

Staff SoC Design Engineer with 10+ years of experience.Model analog blocks in System Verilog Real Number Modelling (SVRNM) and Verilog AMS and verify digital blocks by creating highly reusable test bench architecture in UVM.Wear two hats one of a Design Verification Engineer when using UVM and as an Analog Circuit Designer when modelling analog blocks using SVRNM & Verilog AMS. Hence, Analog and Mixed-Signal Design Verification Engineer!Have done AMS Verification of numerous highly complex mixed-signal SoCs in advanced nodes for cutting edge applications (5G, AI, ADAS, Car Infotainment, and Networking)Have verified the following mixed-signal blocks using UVM-MS as the methodology:• Multi-protocol PHYs (PCIe, DDR, Ethernet, USB, SATA, BLE, Zigbee, and HDMI)• ADCs• DACs• PLLs• PMICsCurrently working on AMS Verification of a SOC which has several Analog and Digital IPs & VIPs with complex interactions between them.• Experience in SoC & IP level verification of Analog Mixed Signal Designs.• Experience in Behavioral Modelling of Analog Blocks.• Deep knowledge of System Verilog testbench language, UVM & UVM-MS.• Hands-on experience with constrained random & coverage driven verification environments.• Hands-on experience with assertions-based Verification. • Good understanding of protocols like AMBA (ACE, AXI, AHB, APB), DDR4, DDR5, Ethernet, PCIe, I2C, SPI, and UART.• Experience in simulations in Cadence Tools like Virtuoso, Spectre, Spectre X, APS, XPS, AMS Designer, Incisive, Xcelium.• Experience in simulations in Synopsys Tools like VCS-AMS, VCSMX, XA, Hspice, DVE, Verdi, nWave. • Good understanding of System-level Test bench Architecture and Verification flow at the System level.• Proficient in both functional and gate-level simulations.• Exposure to the preparation of test plan and architecture document.• Superior debugging & documentation skills.• Excellent communication skills, analytical skills, and result-oriented as an individual and in a team. • Willing to learn new skills and the ability to learn fast.Specialties: Semiconductors, UVM-MS, UVM, System Verilog, SVRNM, VAMS Wreal, Analog & Digital Design, SerDes, PMIC, Data Converters, PCIe, Ethernet, DDR, AMBA, I3C, I2S, SOC Verification, Scripting, EDA tools, AI, Leading teams, Managing people, Mentoring & Nurturing young talent.

Experience

1. Staff Soc Design Engineer

   Intel

   Feb 2022 — Present

Education

• Muffakham Jah College Of Engineering And Technology

  Master of Engineering (M.Eng.), VLSI

  2012 — 2014

• Jawaharlal Nehru Technological University

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2007 — 2011

Skills

• Customsim
• Cadence Virtuoso
• Cadence Spectre
• Perl
• Analog & Mixed Signal Verification
• Analog Circuit Design
• Universal Verification Methodology (Uvm)
• Vcs
• Cadence Ams
• Cadence(Spectre,Spectre Rf,Analog Artist,Virtuoso,Ams )
• C
• Mixed-Signal Ic Design
• System Verilog Assertions
• Verilog-Ams
• System Verilog
• Asic
• Systemverilog
• Rtl Design
• Wreal
• Vlsi
• Vcs-Ams
• Vcs-Xa
• Verdi-Ams Debug
• C++
• Verilog
• Uvm
• Semiconductors
• Verilog-a
• Functional Verification
• Very-Large-Scale Integration (Vlsi)