Mohammed Yassine Kaabouch

Asic Verification Engineer @ELSYS Design

Defining the Architecture of the Test Bench • Development of a verification environment: scoreboard, coverage, Assertions, sequences, tests. • IP Verification Integration • Formal verification (Elaboration and Autocheck). • Code coverage Analysis for the IP to increase togglebranch, statement, FEC-condition and expression, design FSM. • Creation of the IP_XACT by IdesignSpec tools. • Generation and Integration of the RAL (UVM Registers Models)