Mohammad Suheb Zameer

About Mohammad Suheb Zameer

Working at Qualcomm, Snapdragon SOC team on UVM, C based test benches and architecture Worked at Microsoft, I worked on DDR subsystem verification including UVM test benches, constraint-randomisation, coverage.Previously at Cadence, I worked as a Field Application Engineer for DisplayPort, AMBA Verification IPs supporting major customers in Silicon Valley.Graduated in ECE, September 2017 - June 2019 Skills : Verilog, SystemVerilog, UVM, C, Shell, Python, Emulation, Verification, Formal Verification, Debugging, DFT, STATools : Questa sim, VCS, Veloce Solo, Xilinx ISE, Virtuoso, Calibre, Design CompilerHands on experience with Linux.Courses taken at Portland State UniversityWinter 2019:Formal VerificationLow Power IC DesignFall 2019:Advanced Computer ArchitectureSpring 2018:Computer ArchitectureFundamentals of Pre-Silicon ValidationWinter 2018:ASIC Modeling and SynthesisIntroduction to SystemVerilogFall 2017:Microprocessor System DesignDigital Integrated Circuit Design-I

Experience

1. Soc Verification, Staff

   Qualcomm

   Aug 2025 — Present · Santa Clara, CA, US

Education

• JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA

  BACHELOR OF TECHNOLOGY, Electrical, Electronics and Communications Engineering

  2009 — 2013

• Delhi Public School Greater Noida

  High School

• Portland State University

  Master of Science - MS, Electrical and Computer Engineering

  2017 — 2019

Skills

• Computer Architecture
• C
• Programming
• Microcontrollers
• Uvm
• Systemverilog
• Powerpoint
• Microsoft Excel
• Html
• Microsoft Office
• Vlsi
• Microsoft Word
• Electronics
• Dft
• Matlab
• Application-Specific Integrated Circuits (Asic)
• Linux
• System Verilog
• Microsoft Powerpoint
• Vhdl
• Verilog
• Debugging
• Fpga
• Leadership
• Embedded Systems
• Static Timing Analysis
• Management
• Very-Large-Scale Integration (Vlsi)
• C++
• Team Motivation