Mohammad Aatif Momin

About Mohammad Aatif Momin

6+ years of experience in SOC RTL Design where working in power team for UPF design based on the specification for Modem Subsystem in SOC and Clock Management IPs owner that follows responsible for clocks generation for multiple IPs, Clock tree diagram and ARM low power interface protocol also performed RTL sanity checks (compile, Lint, CDC, VCLP). Supporting Design Verification team, Physical Design Team and Software team in achieving the good quality of IP. Currently I am working in Modem Subsystem handling UPF and Clock Management IPs to support power reduction and performance metrics of Modem Subsystem. Additionally, contributing to memories selection and memory generation for multiple IP to balance power, performance, and area (PPA) requirements. A proactive team player with strong methodology and automation knowledge that helps me and team to work very efficiently.

Experience

1. Staff Engineer

   Samsung Electronics

   Nov 2022 — Present · IN

   Working for Power Arcitecture Team-Owning UPF for SoC-Learning Power management strategy for SoC

Education

• Government Polytechnic Mumbai

  Diploma, Electronics Engineering

  2010 — 2013

• Vellore Institute of Technology

  Master of Technology - MTech, VLSI Design Engineer

  2017 — 2019

• Vasantdada Patil Pratishthan’s College of Engineering and Visual Arts (VPPCOEVA)

  Bachelor of Engineering - BE, EXTC Engineer

  2013 — 2016