Muhammad Obaidullah
Senior Asic Design Engineer @高通
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WORK HISTORY
Senior Asic Design Engineer @高通
Richmond Hill, ON, CA
Working on future Snapdragon SoCs for Mobile and PCs.Worked on Snapdragon 4 Series (for entry-level smartphones) to Snapdragon 8 Gen 3+(2024 High-end smartphones)
EDUCATION
Syscoms Computer Institute
Completion Certificate, C++ Programming Course
Islamia English School
A-Level, Science
Abu Dhabi University
Bachelor of Science (B.Sc.), Electrical Engineering minor in Computer Engineering
Ryerson University
M.A.Sc. Electrical and Computer Engineering, Interconnection Networks (Network-on-Chip)
Areef Computer Institute
Certificate
SKILLS
ABOUT MUHAMMAD OBAIDULLAH
Over the past years, I have been researching in System on Chip (SoC) and Network on Chip (NoC) design. I have majored in Electrical Engineering (communication) and became interested in advanced NoC application mapping and synthesis optimization techniques. I have developed a new and specially tailored optimization technique for NoC application mapping problem which is a hybrid of Tabu-Search and Particle Swarm Optimization methods.The main objective of developing Network on Chips is for IC designers to cut their design time very short. IPs available nowadays have different interconnect specifications eg. AMBA, Avalon, STBus etc. and these limit the number of cores and IPs on single chip because of limited control lines available. Additionally, if addition of control lines is done, complexity of the chip increases exponentially. To deal with complexity, abstraction and regularity of design is required. There is a need to design network for interconnection of these cores if the technology is to move ahead of octa-core domain.In addition to this, I am also researching on how to accelerate different optimization algorithms by use of Heterogeneous Processing Units running parallel code (OpenCL Kernels). GPUs in recent years have shown their vector processing capabilities and GPU vendors (Nvidia, Intel, and AMD) provide APIs to use these parallel processing features. Several existing algorithms and optimization techniques can be accelerated by use of parallel heterogeneous processing.
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