Mohd Sajid Khan
Premium Rtl Design and Verification Course @Vlsi For All Pvt Limited
Pilibhit, UP, IN
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WORK HISTORY
Sep 2024 — Present
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Digital IC Design | STA | Verilog | CMOS Design | System Verilog | UVM | Perl language | Linting | COA | Digital Electronics.
EDUCATION
N/A
Saraswati Vidhya Mandir
CLASS XII
2020 — 2022
Jamia Millia Islamia
Master of Science - MS
2016 — 2018
Mahatma Jyotiba Phule Rohilkhand University
Bachelor of Science - BS
2023 — 2025
Indian Institute of Technology, Kharagpur
Master of Technology - MTech
N/A
Saraswati Vidhya Mandir
CLASS X
2020 — 2022
Jamia Millia Islamia
Master's degree
ABOUT MOHD SAJID KHAN
I am a postgraduate electronics engineer with a strong foundation in digital design…
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