Mohd Sajid Khan
Aspiring RTL/Design Verification Engineer | M.Tech ’25 – IIT Kharagpur | M.Sc. Electronics – Jamia | VLSI Trainee @ VLSIFORALL | Verilog | System Verilog | UVM | STA | FPGA |SILVACO TCAD | DEVICE MODELLING| FABRICATION
- Role
- Premium Rtl Design and Verification Course at Vlsi For All Pvt Limited
- Location
- Pilibhit, UP, IN
- LinkedIn followers
- 500 followers
About Mohd Sajid Khan
I am a postgraduate electronics engineer with a strong foundation in digital design…
Experience
Premium Rtl Design and Verification Course
Sep 2024 — Present
Digital IC Design | STA | Verilog | CMOS Design | System Verilog | UVM | Perl language | Linting | COA | Digital Electronics.
Education
Saraswati Vidhya Mandir
CLASS XII
Jamia Millia Islamia
Master of Science - MS
2020 — 2022
Mahatma Jyotiba Phule Rohilkhand University
Bachelor of Science - BS
2016 — 2018
Indian Institute of Technology, Kharagpur
Master of Technology - MTech
2023 — 2025
Saraswati Vidhya Mandir
CLASS X
Jamia Millia Islamia
Master's degree
2020 — 2022
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