Mahesh Malewale
STA Engineer @ Intel Corporation | MTech in VLSI Design
- Role
- Sta Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Mahesh Malewale
Intel Corporation leverages expertise in static timing analysis to optimize System-on-Chip (SoC) designs. As an STA Engineer, collaborated with cross-functional teams to ensure timing closure and design reliability for advanced semiconductor products. Contributions are informed by a strong academic foundation in VLSI Design and Embedded Systems from NIT Raipur. Prior experience at GLOBALFOUNDRIES as a Physical Design Intern enhanced understanding of physical implementation workflows. Education and professional journey are rooted in a commitment to innovation and precision in semiconductor design. Emphasis is placed on enabling efficient, high-performance chip solutions.
Experience
Sta Engineer
Feb 2021 — Present · Bangalore Urban, IN
Education
Yeshwant Mahavidyalaya, Nanded
Higher Secondary School
2011 — 2013
Madhavrao Patil Highschool, Nanded
Schooling
2001 — 2011
Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded
B.Tech
2013 — 2017
National Institute of Technology Raipur
Master of Technology - MTech (Hons)
2018 — 2020
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.