Michael Kulikowski

Experience

1. Senior Principal Test Engineer, Ccs Custom Cloud Solutions

   Marvell Technology

   Apr 2026 — Present · Burlington, VT, US

   Technical lead for advanced semiconductor test architectures, supporting complex SoCs from early silicon through high‑volume manufacturing- Defined test strategies for 2.5D integration, HBM (High Bandwidth Memory), and multi‑die packaging- Led validation and production test of high‑speed SERDES and complex communication PHY IPs, including protocol‑based testing- Architected scalable ATE test solutions enabling parallel test, reuse, and efficient ramp to production- Partnered with design and DFT teams to influence testability, coverage, and observability early in the design cycle- Developed reusable test IP, automation frameworks, and datalog standards (STDF) using Java and Python- Supported silicon bring‑up, debug, yield analysis, and test program migration across multiple device generations- Acted as a cross‑program technical leader, mentoring engineers and coordinating test strategy across teams and vendors

Education

• Vermont Technical College

  AS, Electrical Engineering

  1997 — 1999

• University of Vermont

  BS, Electrical Engineering

  2000 — 2004

Skills

• Characterization
• Reliability
• Semiconductor Test
• Semiconductor Manufacturing
• Semiconductors
• Sas
• Vlsi
• Soc
• Dft
• Integration
• Embedded Systems
• Analog
• Hardware Architecture
• Testing
• Verilog
• Sql
• Teradyne
• Dram
• Mixed Signal
• Circuit Design
• Ic
• Sram
• Manufacturing
• Debugging
• Edram
• Microprocessors
• Test Equipment
• Failure Analysis
• Dram Characterization
• Semiconductor Industry
• Processors
• Cmos
• Memory Test
• Asic
• Bist
• Automation
• Yield