Muhammad Kazim Hafeez

About Muhammad Kazim Hafeez

Professional Experience-• High Tech industry experience in IP\'s Design as well as Embedded Systems Design.• Pioneer and key contributor in defining the innovation idea over E-Tile Stratix10 FPGA and brought it into reality for next generation Dynamic Reconfiguration framework for Agilex7 FPGA F-Tile Transceiver based design IPs by collaboration with software and hardware architects. • Hands on experience to Lead team and involved in work estimation, planning, prioritizing tasks, scheduling, resource allocation meeting, discussion and progress tracking. • Developed micro-architectures for various designs.• Provided customer support in various projects. • Designed and developed RTL for 8051, 80251 compatible micro-controllers cores, AMBA Buses(APB, AXI), USB2.0, SmartUART, LZW, RTC, I2C, SPI, LCD, PalmBus, MBus, NAND Flash controllers and HMCC(Hybrid Memory Cube controller), E-Tile 10G/25G Ethernet Intel FPGA hard IPs, Ethernet Universal Traffic Generators and Checkers, F-Tile Dynamic Reconfiguration Intel FPGA IPs in Verilog HDL.• Worked on the development of Universal NAND flash model in System Verilog as well as in C. • Developed Sourcery CodeBench Virtual Probe features in embedded C, vDAP/vJTAG Transactors developed for Veloce emulation platform and complex SoC development (CortexAx based microcontrollers) over Veloce Platform in SystemVerilog.• Developed hardware abstraction layer (HAL) interface for an ARM based design, as well as power on self tests for the design.• Developed various verification routines in C/Assembly for the verification of a 8051 and 80251 compatible cores.• Also worked on the development of layer II protocols like LLDP and also integrated RSTP protocol in firmware for UWB based set top products. Development of.NET GUI for configuration of UWB based set top product. • Implemented the SCSI Command set and related Unit tests in Python to be used for the performance testing of a SSD. • Developed various modules (network control and security) of HomePlug Green PHY standard and also worked on implementation of application layer modules of SEP2.0 (RESTFul HTTP server/client) in embedded C, integrated with sockets and XML datastore.

Experience

1. Software (Rtl) Enabling and Optimization Engineer

   Altera

   Jan 2025 — Present · San Jose, CA, US

Education

• COMSATS Institute of Information and Technology

  BS/BE, Computer Engineering

  2003 — 2007

Skills

• Uvm
• Integrated Circuit Design
• Hardware Architecture
• Verilog
• Assembly
• Firmware
• Xilinx
• Systemverilog
• Questa
• Field-Programmable Gate Arrays (Fpga)
• I2c
• Microcontrollers
• Shell Scripting
• Hardware
• Rtl Design
• Fpga
• Socket Programming
• Asic
• C++
• Matlab
• Arm
• Vcs
• Emulator
• Altera Quartus
• Computer Architecture
• Perl
• Embedded Systems
• Testing
• C
• Programming
• Debugging
• Digital Signal Processors
• Spi
• Keil
• Veloce
• Usb
• Systemc
• Modelsim
• Python
• Soc