Miti Joshi
Sr. Design Engineer 1 at Xilinx
- Role
- Sr Design Engineer 1 at Xilinx
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Miti Joshi
Experienced 4+ years in the industry. Open for an exciting opportunity.
Experience
Sr Design Engineer 1
Nov 2018 — Present · Hyderabad, IN
Education
GOVT. ENGG.COLLEGE GANDHINAGAR
B.E.
2008 — 2012
Gujarat Technological University
Master of Engineering (M.Eng.)
2012 — 2014
Skills
- Vhdl
- Verilog
- Functional Verification
- Mentor Graphics Questasim
- Integrated Circuit Design
- Embedded C
- Universal Verification Methodology (Uvm)
- Very-Large-Scale Integration (Vlsi)
- Cmos
- Perl Script
- Logic Design
- Rtl Verification
- Perl
- Physical Design
- Application-Specific Integrated Circuits (Asic)
- Amba
- Tcl
- Xilinx
- Systemverilog
- C++ Language
- Xilinx Ise
- Multisim
- Synopsys Tools
- System Verilog
- Rtl Design
- Linux
- Modelsim
- C++
- Vlsi
- Asic
- Rtl Coding
- Keil
- Logic Synthesis
- Amba Ahb
- C
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.