Mithesh K

About Mithesh K

Validation Engineer with expertise in high-speed SerDes (28G, 56G, 112G, PCIe Gen5), HBM3, and GDDR6 memory technologies. Skilled in silicon validation, protocol compliance, system bring-up, and debug across advanced semiconductor IPs.Proficient in SI/PI validation, including S-parameter extraction, PHY return loss analysis, jitter/eye margining, and mixed-signal characterization. Experienced with BERTs, PNAs, spectrum analyzers, and high-speed oscilloscopes for interface validation and system debug.Led electrical validation of SoundWire, I²S, and I³S interfaces across customer projects, managing a 2-member team. Additional experience in PCB schematic design and Cadence PCB tools for board-level validation and hardware integration.Education: • M.Tech, Microelectronics – BITS Pilani • B.E, ECE – PES University

Experience

1. Lead Design Engineer

   Cadence

   Jul 2024 — Present · Bengaluru, IN

   HBM3E PHY/DRAM silicon validation, focusing on training mechanisms, timing alignment, and protocol compliance.• Owned electrical validation of Soundwire, I²S, and I³S interfaces for three customer projects; managed two engineers and delivered customer-ready results on schedule.• Performed board-level signal integrity characterization, including S-parameter extraction and PHY return loss analysis, correlating board-level effects with PHY behavior.• Extensive use of BERTs, spectrum analyzers, Keysight PNA, and high-speed oscilloscopes for validation and debug of high-speed interfaces.• Driving mixed-signal debug and system bring-up, collaborating with design and architecture teams to achieve first-pass silicon success.

Education

• K.L.E. Society's S. Nijalingappa College (KLE SNC), Bengaluru

  Pre University, PCME

  2012 — 2014

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech, Microelectronics

• PES University

  Bachelor of Engineering - BE, Electronics and Communications Engineering

• Assumption English School

  SSLC

  2012