Miraj Tadhani

About Miraj Tadhani

Experienced ASIC/FPGA design engineer skilled inDevelopment, verification and validation RTL design for FPGA prototyping IPs Time domain multiplexing (TDM) IP, muti-gigabit GTH/GTY transceiverDesign Bringup of PCIe, DDR3/4, SerDes for High Performance banks, MIPI CSI/DSI on VU440 xilinx FPGAs Block level verification of IP using directed SV testbench, UVM testbenches, constrained random sequence, system verilog assertionsExperience developing complex block level design consisting Zynq PS, AXI Lite, stream interface, BRAM, DMA engine, Xactors, MIG DDR3/4, VDMA components Experience developing Image processing filters using high level XILINX vivado (HLS) and OpenCV librariesExperience in SoC design partitioning for multi FPGAs system implementation Programming Skills : Verilog (HDL), System Verilog, Python, C, C++, Tcl, Assembly language Digital Logic Design: Proficient in RTL Design (using Verilog & SystemVerilog), RTL SimulationSynthesis and gate-level netlist generation, Place and route, Static Timing Analysis(STA), ClockDomain Crossing issues and Synchronization Strong understanding of RISC and CISC processor & Memory Systems concepts: Cache Organization, Verification Methodologies using System Verilog: UVM Tools : ASIC Design- Synopsys VCS, ModelSim, Design Compiler, Synopsys Primetime, GTKWave, NC-Verilog, Xilinx Vivado, QuestaSim Bus Protocols: SPI, UART, I2C, AMBA APB, AHB, AXI (Lite, stream, memory mapped) Version Control: Perforce, Git

Experience

1. Staff Engineer

   Samsung Semiconductor

   Mar 2025 — Present · Austin, TX, US

Education

• San José State University

  Master of Science (MS), Digital System Design(Electrical Engineering)

  2016 — 2018

• Dharmsinh Desai University

  Bachelor’s Degree, Electronics and Communication Engineering

  2009 — 2013

Skills

• Matlab
• Plc Programming
• C
• C++
• Programming
• Engineering
• Powerpoint
• Project Management
• Microcontrollers
• Python
• Verilog
• Vhdl
• Assembly Language
• Hmi Design
• Rtl Design
• Cmos
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• System Verification
• Constraint Rendomization
• Avr Studio 4
• Express Pcb
• Universal Verification Methodology (Uvm)
• Xilinx Vivado
• Logic Synthesis
• Fpga Design
• Clock Tree Synthesis
• Perl Automation
• Object-Oriented Programming (Oop)
• Arm Architecture
• Mips Instruction Set
• Nios Ii
• Cadence Virtuoso
• Digital Ic Design
• Timing Closure
• Static Timing Analysis
• Axi
• Assertion Based Verification
• Code Coverage
• Functional Coverage