Minqi

WORK HISTORY

EDUCATION

ABOUT MINQI

Strong knowledge in ISP (Image Signal Processor) and Assertive Display ASIC IP design- Strong knowledge in low power IP design- Strong knowledge in ASIC and Multi-Cores SOC design- Proficient in RTL design with System Verilog / Verilog HDL / VHDL- Proficient in Fixed point modeling from the floating point algorithm with Matlab or C/C++- Proficient in CDC clock domains crossings design, analysis, and meta-stability injection verification flow / methodology creation- Proficient in FPGA implementation for ASIC proto-type and algorithm performance test- Proficient in Multiple FPGAs implementation for the complex SOC proto-type- Proficient in SoC low power design- Proficient in physically aware Synthesis (DC topo) and STA- Familiar with TI VBUSM / VBUSP, AMBA (AXI, AHB, APB), and PIF bus protocols- Familiar with Matlab and C/C++ in ISP and DSP algorithm design- Familiar with asynchronous logics design in ultra low power embedded processors- Familiar with Multiple Cores SOC verification- Familiar with DDR PHY, memory controller and the related integration- Familiar with RapidIO, Serdes and the related integration- Familiar with the MPEG-2 video decoder, including C modeling and RTL coding- Familiar with the IF Receiver design of the digital video broadcast standards: DVB-C, ATSC, including architecture / algorithm design, RTL design and silicon implementation- Familiar with the algorithm and RTL design of QAM, 8-VSB IF demodulators, Timing Recovery, Carrier Recovery with the FPLL, Reed-Solomon decoder of the above two standards.