Minjal Patel
MTS Silicon Design Engineer
- Role
- Mts Silicon Design Engineer at AMD
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Minjal Patel
SKILLS:Operating Systems: Windows, LinuxProgramming and Scripting Languages: C/C++, PerlHDL and HVL Languages: Verilog, System VerilogMethodology: UVM, Client’s proprietary Coverage Driven Validation MethodologyEDA Tools: Verilog Compiler Synopsys (VCS), Cadence VManager and ICCR, Cadence Simvision waveform viewerVersion Control Tools: Perforce, CVS, Rational ClearcaseBus Protocol: APB, PCI, I2C, AHB, SATA
Experience
Mts Silicon Design Engineer
Jul 2024 — Present · San Jose, CA, US
Education
UNSW
Master of Engineering Science (MEngSc), Microelectronics & Microsystems
2009 — 2010
San José State University
Master's degree, Electrical Engineering
2013 — 2015
Skills
- Matlab
- Teamwork
- Team Management
- C++
- Vhdl
- Simulations
- C
- Xilinx
- Systemverilog
- Microsoft Office
- Perl
- Eda
- Microsoft Excel
- Uvm
- Fpga
- Asic
- Verilog
- Engineering
- Sv
- Linux
- Debugging
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