Mini Rawat
Senior ASIC Design Engineer at NVIDIA
- Role
- Senior Asic Design Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Mini Rawat
Seasoned Engineer with 15 years of experience in Hardware Design and Semiconductor Technology focused on Architecture, Performance/Power Optimizations and Digital Circuits. Delivered cutting edge micro processor chips, all programmable gate array & GPU chips. My key focus areas are: ML/AI chip design with specialization in accelerators, L2/L3 Caches in GPU hardware, Physical Design and Floor Planning optimizations, Data Center GPU Cluster efficiency optimizations, Reliability and Signal Integrity in chips, Energy efficient processor design, PPA optimizations, pre/post-Silicon Technology and Silicon & hl=en
Experience
Senior Asic Design Engineer
Oct 2018 — Present · San Francisco, CA, US
PPA optimizations, GPU design, Silicon design
Education
Stanford University
Artificial Intelligence
Madan Mohan Malviya Engineering College,Uttar Pradesh
B-Tech, Electronics & Communication Engineering
2005 — 2009
The University of Texas at Dallas
Master of Science (MS), Electrical Engineering -Circuits & Systems
2011 — 2012
Skills
- Analog
- Integrated Circuit Design
- Analog Circuit Design
- Vhdl
- Sram Design
- Verilog
- Eda
- Computer Architecture
- Spectre
- Rtl Synthesis
- Static Timing Analysis
- Low-Power Design
- Cadence Virtuoso
- Vlsi
- Soc
- Asic
- Circuit Design
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