Ming Cheung

About Ming Cheung

Physical Design Engineer with 10+ years of project management (schedule, cost, and…

Experience

1. Cadence

   Present

Skills

• Logic Synthesis
• Cadence Virtuoso
• Noise Analysis
• At Speed Atpg
• Power Switches
• Global Foundry 28nm Asic Design
• Arm Standard Cell Libraries
• Verilog Test Benches
• Flip Chip Bump Design
• Gdsii
• Arm 9
• Cadence Rc and Genus Tool for Logic Synthesis & Dft Insertion
• Pcie Ip
• Ddr3 & Ddr4 Ip
• Arm7
• Static Timing Closure (Sta)
• Verilog
• Hspice Simulations
• Cpu Design
• Celtic Noise Analysis
• Encounter Place & Route Tool of Cadence Design Systems
• Primetime Sta Analysis Tool of Synopsys
• Chemical and Mechnical Polishing
• Cpf
• Memory Controllers
• Dft Compiler
• Model-Sim From Mentor Graphics
• Tsmc 40nm Asic Design
• Calibre for Physical Verifications
• Rc Compiler
• Tsmc 28nm Asic Design
• Conformal Lec
• Ir Drop Analysis
• Structural Data Path Placement
• Fpga
• Mips Processors
• Mbist
• Encounter Timing Systems of Cadence
• Jtag
• Tensilica Cpu