Min Fu
Soc Ip Designer @Intel
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WORK HISTORY
Soc Ip Designer @Intel
Vancouver, BC, CA
Intel IPU- NVMe over Fabric protocol- Smart End Point- Microarchitech-design- ECO. Timing Closure- Emulation/RTL2Gate/LEC Flows enablement- Collaborate with back end Team for tape out.
EDUCATION
Université de Montréal
Master of Science (MS), Computer Science
Beijing Institute of Technology
Master of Engineering (MEng), Electrical and Electronics Engineering
SKILLS
ABOUT MIN FU
Full cycle ASIC design, micro-architect design.– Cross-functional team collaboration. – IPU/SmartNIC; SSD controller; Telecommunication Router; Image Processing; Signal Processing.– SoC Emulation system development with Low Power UPF implemented.– ARM SoC co-verification, firmware and driver development.– Full FPGA design flow: Architecture design, RTL coding, Synthesis,Timing Analysis and Constraints– RTL verification, UVM, technical documentation.– Machine Learning Algorithm accelerated on FPGAs: accelerate object detection algorithm by FPGA implementation.
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