Min Pan

Experience

1. Sr Director of Research Development

   Synopsys Inc

   Jun 2008 — Present · Sunnyvale, CA, US

   Leading the highly skilled R&D team at 7 different sites around the globe in US, Europe, China, India and Taiwan to solve the most challenging EDA optimization problems. Technically leading the technology innovation for the market leading Digital Implementation products (Fusion Compiler / IC Compiler II), specially in the domain of clocking methodology, clock tree synthesis/optimization, and concurrent clock and data optimization.Expertise in clock tree synthesis, concurrent clock and data optimization, placement and routing algorithms, machine learning, EDA on cloud. Very familiar with the full digital IC implementation flow and system including placement, routing, optimization, timing, extraction, etc.Closely collaborating with AI Leaders such as Nvidia, AMD, Google, Microsoft, etc. to build the most advanced AI systems with AI-driven EDA solutions.

Skills

• Verilog
• Vlsi
• Tcl
• Ic
• Low-Power Design
• Algorithms
• Physical Design
• Asic
• Optimization
• Clock Tree Synthesis
• Place & Route
• Soc
• Debugging
• Perl
• Eda
• Static Timing Analysis