Mike Evans

About Mike Evans

ASIC industry veteran with a wide breadth of experience across more than 17 years in the silicon development domain: 4 years of enabling post-silicon performance bring-up. 2 years of building and leading a new digital design team and driving the architecture for prototype nanophotonic AI processors. 8 years of aggressive, high-performance digital logic design and block-level micro-architecture in GPUs. 3 years of focus in digital logic design and P&R supporting low-power ASICs in mobile devices. Adaptable generalist with knowledge and experience across several domains. Frequently leveraged at critical checkpoints, including product conceptualization, patent generation, etc.Awarded patents across multiple domains: ASIC Architecture AI Model Design VR DisplaysExperienced Digital Design Methodology System Verilog. RTL designed to be safe, explicit, and easy for others to read and understand. Forward-thinking, flexible, and long-lasting implementations. Careful attention paid to Power vs. Area vs. Performance tradeoffs. Micro-architected to best exploit the advantages of the target fabrication process. ASIC implementation flow experience: Synthesis. Timing closure. Place & Route. Netlist-level and P&R-level ECOs. Design Verification. Test Bench design.

Experience

1. Principal Member of Technical Staff

   AMD

   Jun 2023 — Present · Boxborough, MA, US

Education

• Georgia Institute of Technology

  BSEE, Electrical Engineering (Digital ASIC design/layout)

  2001 — 2006