Mihir Shah
Principal FPGA Design Engineer at Cadence Design Systems
- Role
- Principal Fpga Design Engineer at Cadence
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Principal Fpga Design Engineer
Feb 2024 — Present
Education
SRM IST Chennai
Bachelor's degree, Mechatronics Engineering
2010 — 2014
The University of Texas at Dallas
Master's degree, Electrical and Computer Engineering
2015 — 2018
Skills
- Pro-Engineer
- C++
- Fpga
- Embedded Software
- Verilog
- Pspice
- Vhdl
- Simulations
- Pcb Design
- Embedded C
- Microcontrollers
- Ansys
- Algorithms
- Python
- Mechatronics
- Solidworks
- Vlsi
- Embedded Systems
- Linux
- Very-Large-Scale Integration (Vlsi)
- Signal Processing
- Simulink
- Testing
- Matlab
- Electrical Engineering
- Pro Engineer
- C
- Programming
- Electronics
- Labview
- Robotics
- Machine Learning
- Digital Electronics
- Microprocessors
- Vlsi Cad
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