Mihir Bedekar
Design Engineer 11 @Cadence Design Systems》 M.Tech(Embedded Systems)from BITS,Pilani WILP 》B.Tech (Electronics) from WCE,Sangli 》Former Vice President WCE ELESA(Student Association).
- Role
- Design Engineer Ii at Cadence
- Location
- Sangli, MH, IN
- LinkedIn followers
- 500 followers
About Mihir Bedekar
Design engineer II at Cadence Design Systems Pune with 3 years experience-> Experienced in subsystem level TLM Modelling-> Demonstrated team Leading qualities while working as Vice President for Technical Student Association at WCE ELESA.
Experience
Design Engineer Ii
Jan 2025 — Present · Pune, IN
Actively involved in Designing Performance Model for Cadence Chiplet project. involves modelling of -NOC components-LPDDR5 memory controller
Education
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech, Embedded system
Walchand College of Engineering(A Govt. Aided Autonomous Institute),SANGLI-M.S
Bachelor's degree, Electronics
2018 — 2022
Adarsh Shikshan Mandir,Miraj
SSC
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