Michael Naumann

FPGA Design and Embedded Engineer at CoMind | Experienced FPGA Designer | RTL Development with DSP | Specializing in High-Performance Embedded Systems

Role
Fpga Design and Embedded Engineer at CoMind
Location
Raleigh-Durham-Chapel Hill, NC, US
LinkedIn followers
500 followers

Experience

  1. Fpga Design and Embedded Engineer

    CoMind

    Aug 2022 — Present · Raleigh, NC, US

    Build a proof of concept acquisition and streaming system for non-invasive neuroimaging, specifically targeting a Xilinx Kintex Ultrascale+ FPGA. Assess the viability and cost implications associated with delegating computational workloads to the FPGA and propose alternative system architectures and form factors for medical trials.• Design and port the configuration procedure for internal and external peripherals to FPGA using C, leveraging the Xilinx softcore MicroBlaze (SPI, JESD, Memory-Mapping)Implement JESD204B and synchronization across four lanes at 10 Gbps, thereby allowing successful acquisition from ADCs• Enhance XDMA PCIe driver functionality by developing RTL modules and implementing AXI crossbar mapping, expanding the capabilities of the software API• Integrate and validate HLS DSP modules using a fixed-point software parallel model• Develop a data-flow architecture for a segment of DSP operations managed on the host machine, establishing bandwidth specifications between architectural blocks• Evaluate DDR4 simulation read/write speeds by comparing random and sequential access patterns to assess the computational viability of the architecture

Education

  • Duke University

    Bachelor of Science, Electrical and Computer Engineering, Certificate in Markets and Management Studies

  • Pinewood High School

    High School

  • Duke University

    Master of Engineering, Electrical and Computer Engineering

    2022 — 2023

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Michael Naumann — Fpga Design and Embedded Engineer at CoMind in Raleigh-Durham-Chapel Hill, NC, US | Unifers