Mahatru Guddamsetty
Electrical Engineering at University of California, Riverside - Bourns College of Engineering
- Role
- Independent Verilog Design Projects at Highlander Racing
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Mahatru Guddamsetty
Hi! My name is Mahatru Guddamsetty, and I currently study electrical engineering as a…
Experience
Independent Verilog Design Projects
Jul 2025 — Present
Designing and implementing RTL modules in Verilog, including finite state machines and overlapping/non-overlapping pattern detectors- Verifying the following digital IP blocks: synchronous/asynchronous FIFOs, SPI/I2C interfaces, interrupt controllers, and watchdog timers- Developing parameterized testbenches with clock, duty cycle, and jitter variations- Conducting functional validation through waveform analysis and debugging in Synopsys VCS and Siemens ModelSim
Education
Northwestern University
Pre-Collegiate Summer Institutes, Mechatronics and Electromechanical Design
2023
West Valley College
Dual Enrollment
2020 — 2024
UC San Diego Jacobs School of Engineering
Bachelor of Science - BS, Electrical Engineering
2028
Stanford University
Pre-Collegiate Summer Institutes, Human Computer Interaction
2023
University of California, Riverside
Bachelor of Science - BS, Electrical Engineering
2026
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