Mekhala S Bharadwaj
Qualcomm Inc. | Georgia Tech | Synopsys India Pvt Ltd.
- Role
- Asic Physical Design Engineer at 高通
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Mekhala S Bharadwaj
As an ASIC Physical Design Engineer at Qualcomm, I contribute to advancing SOC designs with a focus on timing, backend design and tiling activities. My role builds on prior industry experience in SRAM memory design, focusing on timing analysis and memory characterization, fostering a strong foundation in VLSI technologies. I am committed to continuous growth and contributing to complex, high-impact engineering problems and collaborating across teams to deliver high-quality results.
Experience
Asic Physical Design Engineer
Mar 2025 — Present · San Diego, CA, US
Education
RV PU College
Pre-University, PCME
2016 — 2018
Georgia Institute of Technology
Master of Science - MS, Electrical and Computer Engineering
B. M. S. College of Engineering
Bachelor of Engineering - BE, Electronics and communication
2018 — 2022
JSS Public School
10th Standard
2016
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